The present invention relates to a decoder which recovers clock and data information from a bit stream.
It is frequently desirable in data processing communication networks to provide a self-clocking data stream in which clocking information is transmitted as an integral part of the data stream. Such data streams are often described as Manchester or bi-phase coded bit streams. In such systems, there is at least one voltage level transition during the period of time allocated to the transmission of each bit; and an additional voltage level transition may also be used during each such bit period to represent binary data. In one such system, a positive-going voltage transition at the start of a bit period represents a 1-bit and a negative-going voltage transition represents a 0-bit. In such a system, if two successive bits are the same, there must be a setup transition in the opposite direction so that the direction of the transition at the start of each bit period is the same. As is known, the transitions of interest can take place at other times than the beginning of the bit period; and the bit value assigned to a specific direction of transition is a matter of choice. In another system, a 0-bit is represented by a bit period having one voltage transition and a 1-bit by a a bit period having two voltage transitions.
Apparatus for recovering data and clock information from a self-clocking data stream is known in the art, being described, for example, in U.S. Pat. No. 3,967,061 which is incorporated herein by reference. The apparatus described in the '061 patent, however, is designed to operate at only 56 Kilobits per second (Kbps), which is relatively slow compared with present day communication standards. For example, in the Ethernet system, data transmission rates are 10 Megabits per second (Mbps); and rates up to 50 Mbps are desirable in some applications.